The present invention generally relates to priority encoders, and more particularly to a reconfigurable priority encoder.
Some content addressable memory (CAM) arrangements include a xe2x80x9cpriority encoderxe2x80x9d circuit. The priority encoder circuit determines, for input data that match multiple entries in the CAM, which entry has the highest priority. The priority of entries in the CAM is generally predefined by the system designer.
Priority encoders generally implement the priority either implicitly or explicitly. Implicit priority uses the physical locations of CAM entries to denote priority. For example, the entry at address 0 has higher priority than the entry at address 1, the entry at address 1 has higher priority than the entry at address 2, and so on. Explicit priority involves codes that are associated with the CAM entries to designate the relative priorities.
Because implicit priority relies on the physical position to denote priority, determining which of multiple matching entries is the highest priority is fast and requires minimal logic. However, adding a new CAM entry involves finding an insertion point in the CAM for the new entry and shifting all lower priority entries to make room for the new entry.
Because explicit priority relies on associated codes to designate priority, new entries can be easily added to the CAM. However, determining which of multiple matching entries is the highest priority is more complex and slower in an explicit priority arrangement than in an implicit priority arrangement. The explicit priority arrangement must sort matching entries, which adds logic and introduces latency.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
The invention provides a reconfigurable priority encoding for identifying, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.